In processors or other integrated circuit devices, such as system-on-a-chip (SoC) devices, static random access memory (SRAM) caches may be provided to store or retain data. In a typical SRAM cache, the bitcells may be subjected to aging stress that leads to a degradation of the read minimum power supply voltage VDDMIN over time. Such degradation may be factored in at the time of designing the device as a flat negative bias temperature instability (NBTI) voltage margin. Aging of the SRAM cache may be an important consideration in the design of processors and other integrated circuit devices due to aging stress of retained data. A typical bitcell in a typical SRAM cache may include one or more p-channel metal oxide semiconductor (PMOS) transistors and one or more n-channel metal oxide semiconductor (NMOS) transistors. In any given state of retention, at least one of the PMOS transistors in the bitcell may be subjected to the aging stress.
In designing integrated circuit devices with SRAM caches, foundries may typically set a very large NBTI voltage margin by assuming the worst case stress conditions throughout the lifetime of the devices and by assuming that there is no recovery from retention failure. In other words, foundries may typically set a very conservative flat guard band for VDDMIN, which is the minimum power supply voltage at which an SRAM bitcell can be reliably read from or written to at a given time. In typical SRAM caches, the minimum power supply voltage VDDMIN may increase over time, for example, over a span of several years, due to aging in the SRAM transistors. Attempts have been made to alleviate the need for overly pessimistic flat guard bands in the design of integrated circuit devices. It would be desirable to devise an aging sensor and a method to measure the aging of an SRAM cache without occupying a large circuit area of the SRAM cache.